Registry

Module Specifications

Current Academic Year 2012 - 2013
Please note that this information is subject to change.

Module Title	Advanced Computer Architectures
Module Code	CA226
School	School of Computing
Online Module Resources
Module Co-ordinator	Semester 1: Ray Walshe Semester 2: Ray Walshe Autumn: Ray Walshe
Module Teacher	Michael Scott
NFQ level	8	Credit Rating	5
Pre-requisite	None
Co-requisite	None
Compatibles	None
Incompatibles	None

Description

The purpose of this module is to introduce participants to modern computer processor architectures. A pipelined 64-bit MIPs architecture will be studied in depth, and used as a vehicle to introduce modern ideas in processor design. A specially developed simulator will be used for hands-on experiments, and as the basis for lab exercises and assignments. The module will further develop the students skill in optimal assembly language programmimg. Students are expected to attend lectures, tutorials and to engage in project work. The module is delivered through a combination of lectures and compulsory Labs.

Learning Outcomes

1. Program in MIPs Assembly Language.
2. Understand how a computer works at the microprocessor level.
3. See how computer architectures are evolving.
4. Predict future trends in architecture design.

Workload	Full-time hours per semester
*Type*	*Hours*	*Description*
Lecture	24	Me talking - them listening
Laboratory	18	Programming exercises
Examination	2	Final Exam
Independent learning time	81	Home work/study/exam & assessment preparation
Total Workload: 125

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

Fundamentals of Computer design.
Classes of Computers. Defining Computer Architecture. Trends in Technology. Quantitative Principles of Computer Design..

Instruction level Parallelism.
Concepts and Challenges. Exposing ILP. Reducing branch costs. Overcoming data hazards. Dynamic vs static scheduling. Speculation..

Instruction set design.
Classifying instruction set Architectures. Memory addressing. Type and size of operands. Encoding an instruction set. The MIPs architecture..

Pipelining.
Pipeline hazards. Implementing pipelining. Why is it so hard? The MIPs 5 stage pipeline. Forwarding..

Assessment Breakdown
Continuous Assessment	40%	Examination Weight	60%

Course Work Breakdown
Type	Description	% of total	Assessment Date
Practical/skills evaluation	Develop an efficient assembly language program	20%	Week 6
Laboratory	Lab. exam. - solve a problem using optimal program	20%	Week 10

Reassessment Requirement
Resit arrangements are explained by the following categories; 1 = A resit is available for all components of the module 2 = No resit is available for 100% continuous assessment module 3 = No resit is available for the continuous assessment component
This module is category 1

Indicative Reading List