Registry

Module Specifications

Current Academic Year 2012 - 2013
Please note that this information is subject to change.

Module Title	VLSI Design
Module Code	EE320
School	School of Electronic Engineering
Online Module Resources
Module Co-ordinator	Semester 1: Xiaojun Wang Semester 2: Xiaojun Wang Autumn: Xiaojun Wang
Module Teacher	Xiaojun Wang
NFQ level	8	Credit Rating	5
Pre-requisite	None
Co-requisite	None
Compatibles	None
Incompatibles	None

Description

This module is intended to introduce students to the basic theory behind the design of large-scale integrated circuits: the configuration of the building blocks, the electrical characteristics of the basic switching circuitry and the design process for translating the circuit onto silicon. The course will also give practical experience in layout design.

Learning Outcomes

1. Explain the principles of the design of standard MOS integrated circuits
2. Outline a standard VLSI design process flow
3. Analyse VLSI circuit performance taking into account the effects of real circuit parameters, including energy, switching speed, noise tolerance
4. Design a basic digital integrated device to specified speed and power and geometrical constraints
5. Use a basic VLSI layout tool
6. Explain the construction of a MOS device and the trade-off between design requirements and manufacturing capability

Workload	Full-time hours per semester
*Type*	*Hours*	*Description*
Lecture	24	2 hours a week
Tutorial	4	Four 1 hour tutorials
Laboratory	25	2.5 hours lab/week for weeks 2 - 11
Independent learning time	67	Self learning of the course material and learn to use the software used for labs
Examination	5	3 hour lab exam + 2 hour written exam
Total Workload: 125

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

Introduction to MOS technology.
Basic electrical properties of MOS and BiCMOS circuits.

MOS and BiCMOS circuit design processes.
Basic circuit concepts.

Scaling of MOS circuits.
Subsystem design and layout.

Examples of design process.

Assessment Breakdown
Continuous Assessment	50%	Examination Weight	50%

Course Work Breakdown
Type	Description	% of total	Assessment Date
Open-book examination	Lab exam	50%	Week 12

Reassessment Requirement
Resit arrangements are explained by the following categories; 1 = A resit is available for all components of the module 2 = No resit is available for 100% continuous assessment module 3 = No resit is available for the continuous assessment component
This module is category 3

Indicative Reading List

Etienne Sicard and Sonia Delmas Bendhia: 2007, Basics of CMOS Cell Design, McGraw-Hill, 9780071488396
John Uyemura: 0, Chip Design for Submicron VLSI: CMOS Layout and Simulation, http://intranet-gei.insa-toulouse.fr/~sicard/microwind/book.html#basic, 9780534466299
Douglas A. Pucknell and Kamran Eshraghian: 1988, Basic VLSI Design: Systems and Circuits, 2nd, Prentice Hall, 0724801057

Other Resources

None

Array

Programme or List of Programmes

BSSA

Study Abroad (DCU Business School)

BSSAO

Study Abroad (DCU Business School)

DME

B.Eng. in Digital Media Engineering

ECSA

Study Abroad (Engineering & Computing)