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Module Specifications

Current Academic Year 2012 - 2013
Please note that this information is subject to change.

Module Title	HDL and High-Level Logic Synthesis
Module Code	EE540
School	School of Electronic Engineering
Online Module Resources
Module Co-ordinator	Semester 1: Xiaojun Wang Semester 2: Xiaojun Wang Autumn: Xiaojun Wang
Module Teacher	Xiaojun Wang
NFQ level	8	Credit Rating	7.5
Pre-requisite	None
Co-requisite	None
Compatibles	None
Incompatibles	None

Description

As system complexity increases, a high-level, top-down design approach becomes essential. The understanding of the top-down design process, and the effective use of standard hardware description languages such as VHDL is therefore important for digital designers. This module introduces the students to the area of high-level logic synthesis from Hardware Description Languages (HDL). It covers HDL modelling for simulation and synthesis, the top-down design process, and the high-level synthesis algorithms that transform an HDL description to its corresponding logic circuits.

Learning Outcomes

1. Write behaviour VHDL models for simulation
2. Write RTL VHDL models for synthesis
3. Use the high-level synthesis techniques
4. Use HDL simulation and synthesis tools
5. Design Digital circuits for implementation with FPGA or ASIC

Workload	Full-time hours per semester
*Type*	*Hours*	*Description*
Lecture	36	3 hours a week
Laboratory	12	Six 2-hour lab session
Assignment	36	An assignment to write a VHDL model according to a design specification, simulate and synthesis the VHDL model
Independent learning	100	Self study on the subject
Examination	3	End of Module Formal Examination
Total Workload: 187

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities

The evolution of VHDL as an industry standard.
VHDL descriptive capabilities.

basic VHDL model structure.
VHDL modelling styles.

modelling of combinational logic.
modelling of synchronous sequential logic.

simulation cycles.
modelling of signal delays.

modelling of finite state machines.
high-level synthesis from HDL.

Design abstraction levels and representation domains.
top-down design process.

high-level synthesis techniques.
control flow graph.

data flow graph.
high level transformations.

scheduling and allocation algorithms.

Assessment Breakdown
Continuous Assessment	25%	Examination Weight	75%

Course Work Breakdown
Type	Description	% of total	Assessment Date
Project	An assignment to write a VHDL model according to a design specification, simulate and synthesis the VHDL model	25%	Week 12

Reassessment Requirement
Resit arrangements are explained by the following categories; 1 = A resit is available for all components of the module 2 = No resit is available for 100% continuous assessment module 3 = No resit is available for the continuous assessment component
This module is category 1

Indicative Reading List

Course notes: 0, available online,
Bhasker, J.: 1996, A VHDL Synthesis Primer, Star Galaxy Publishing, 0965039102
Bhasker, J.: 1994, A VHDL Primer, Prentice Hall, 0131814478
Gajski, D., N. Dutt, A. wu, S. Lin: 1992, High-level synthesis : introduction to chip and system design, Kluwer Academic, 0792391942

Other Resources

None

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CAPD

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M.Eng. in Digital Media Engineering