Registry

Module Specifications

Current Academic Year 2012 - 2013
Please note that this information is subject to change.

Module Title Nano & Microelectronic Device Manufacturing
Module Code EE541
School School of Electronic Engineering
Online Module Resources

Module Co-ordinatorSemester 1: Stephen Daniels
Semester 2: Stephen Daniels
Autumn: Stephen Daniels
Module TeacherStephen Daniels
NFQ level 8 Credit Rating 7.5
Pre-requisite None
Co-requisite None
Compatibles None
Incompatibles None
Description
Module Motivation:An understanding of the processes involved in integrated circuit manufacture is necessary not only in the fabrication process itself but also to appreciate important features and limitations of chip design. This course deals with the physical phenomena which take place during production of multilayer integrated circuits.

Learning Outcomes
1. Design and analyse the processes involved in micro/nanosystems manufacture
2. Calculate important features andlimitations of micro and nano system design
3. Describe basic surface processing tools and their physical interactions during production ofmultilayer ultra-miniaturised devices and circuits



Workload Full-time hours per semester
Type Hours Description
Lecture36No Description
Independent learning time151reading and assignments
Total Workload: 187

All module information is indicative and subject to change. For further information,students are advised to refer to the University's Marks and Standards and Programme Specific Regulations at: http://www.dcu.ie/registry/examinations/index.shtml

Indicative Content and Learning Activities
Basic crystalline structure, defects in crystalsBulk crystal growthDiffusion.
Fick's Laws, atomistic explanation of diffusion, diffusion coefficientsIon implantationOxidation processes, rate controlling factorsLiquid phase, vapour phase and molecular beam epitaxy.Plasma processes: plasma etching & deposition, sputtering, ion beam processingPhysical vapour depositionChemical vapour depositionAssignments:Generally two assignments involving simulations of semiconductor processing schedules..

Chemical Mechanical Polishing.
process and tool descriptions, damancene processing, defects.

Basic plasma technology.
plasma physics introduction, characteristics of plasma tools, interaction with surfaces, diagnostics.

Deposition processes.
Physical vapour deposition, chemical vapour deposition, characteristics of thin films..

Etch Processes.
Basic etching mechanisms, reactive ion etch, selectivity and anisotrophy.

process control.
statistical process control, advanced process control, process metrology.

Miniaturisation.
Moore's Law, design rules, design for manufacture, basic VLSI circuits.

Assessment Breakdown
Continuous Assessment25% Examination Weight75%
Course Work Breakdown
TypeDescription% of totalAssessment Date
AssignmentReview paper on state of the art on an important aspect of semi manufacturing25%Once per semester
Reassessment Requirement
Resit arrangements are explained by the following categories;
1 = A resit is available for all components of the module
2 = No resit is available for 100% continuous assessment module
3 = No resit is available for the continuous assessment component
This module is category 1
Indicative Reading List
  • Gary S. May and Simon M. Sze: 2004, Fundamentals of Semiconductor Manufacturing,
Other Resources
None
Array
Programme or List of Programmes
ECSAOStudy Abroad (Engineering & Computing)
EEVM.Eng. in Electronic Engineering
GCESGrad Cert. in Electronic Systems
GCTCGrad Cert. in Telecommunications Eng.
GDEGraduate Diploma in Electronic Systems
GTCGrad Dip in Telecommunications Eng
IFPESPG Int. Foundation Prog.(Elec. Systems)
IFPTEPG Int. Foundation Prog.: Telecomm.Eng
MENMEng in Electronic Systems
MEQMasters Engineering Qualifier Course
MTCMEng in Telecommunications Engineering
Timetable this semester: Timetable for EE541
Date of Last Revision01-FEB-12
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